ISSCC 2004 / SESSION 21 / 21 . 1 21 . 1 Circular - Geometry Oscillators

Demand for faster data rates in wireline and wireless markets has resulted in tighter jitter and phase noise requirements for oscillators. Although active device noise (and not the resonator noise) dominates the phase noise of most CMOS oscillators [1], in a properly designed oscillator, the quality factor, Q, of the resonant tank indirectly plays a central role in the phase noise. The best phase-noise/power trade-off is usually achieved at the borderline between the currentand voltage-limited regimes. At this operating point, the tank amplitude is proportional to Ibias·Rtank, where Ibias is the oscillator dc bias current and Rtank is the equivalent tank parallel resistance [2]. A higher tank Q translates to a larger effective tank parallel resistance, Rtank. This, in turn, allows the designer to lower the oscillator’s bias current, Ibias, while maintaining the full voltage swing necessary for operation at the edge of the voltage-limited regime. The lower bias current decreases the noise from the active devices, which is the dominant contributor to phase noise. This explains the well-established fact that higher tank quality factor can be used to improve oscillator phase noise.